1. Technical Field
This invention relates generally to memory devices, and more particularly, to resistive memory device operation.
2. Background Art
FIG. 1 illustrates a memory device 30 known as a metal-insulator-metal (MIM) device which includes an electrode 32, an insulating layer 34 (also known as a switching layer) on and in contact with the electrode 32, and an electrode 36 on and in contact with the insulating layer 32, so the insulating layer 34 is between the electrodes 32, 36. The electrode 32 is connected to the drain of an MOS transistor 38, while the source of the transistor 38 is connected to ground, so that the memory device 30 and transistor 38 are in series.
Initially, assuming that the memory device 30 is unprogrammed, high-resistance state, in order to program the memory device 30, a programming voltage Vpg is applied to the electrode 36, so that an electrical potential is applied across the memory device 30 from a higher to a lower potential in the direction from electrode 36 to electrode 32, (see FIG. 2, a plot of memory device current vs. voltage applied to the electrode 36 of the memory device 30). This voltage Vpg is sufficient to cause charge carriers to be moved into the insulating layer 34, causing the insulating layer 34 (and the overall memory device 30) to rapidly switch to a low-resistance or conductive state (A). Upon removal of such potential, the charge carriers moved into the insulating layer 34 during the programming step remain therein, so that the insulating layer 34 (and memory device 30) remain in a conductive or low-resistance state, as indicated by the on-state resistance characteristic (B). The voltage Vga applied to the gate of the transistor 38 determines the magnitude of current through the memory device 30 during the programming step.
In order to erase the memory device 30, a positive voltage Ver is applied to the electrode 36, so that an electrical potential is applied across the memory device 30 from a higher to a lower electrical potential in the same direction as in programming the device 30. This potential Ver is sufficient to cause charge carriers to move from the insulating layer 34, in turn causing the insulating layer 34 (and the overall memory device 30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory device 30. The gate voltage Vgb again determines the magnitude of current through the memory device 30. As illustrated, the erase voltage Ver is lower than the programming voltage Vpg, and the current provided through the memory device 30 during the erase step (C) is higher than the current through the device 30 during the programming step (based on a higher gate voltage during the erase step than during the programming step). Higher gate voltage is usually needed for erase to provide higher current through the device 30 during the erase step.
FIG. 2 also illustrates the read step of the memory device 30 in its programmed (conductive) state and in its erased (nonconductive) state. A voltage Vr is applied to the electrode 36 so that an electrical potential is applied across the memory device 30 from a higher to a lower electrical potential in the same direction as in the programming and erase steps. This voltage Vr is lower than the voltage Vpg applied for programming and is lower than the voltage Ver applied for erasing (see above). In this situation, if the memory device 30 is programmed, the memory device 30 will readily conduct current, indicating that the memory device 30 is in its programmed state. If the memory device 30 is erased, the memory device 30 will not conduct current, indicating that the memory device 30 is in its erased state.
Typically, erasing of a memory device is achieved by applying a fixed number of voltage pulses at constant height across the device 30. Because of physical differences between memory devices in a memory device array, the electrical potential required to achieve erasing can vary between memory devices. Applying a constant erasing electrical potential to a memory device which is substantially greater than that required for erasing can result in overstress of the device. Therefore, what is needed is an approach wherein, while proper erasing of the memory device is achieved, application of excessive unneeded electrical erasing potential is avoided. In addition, the memory device should be structured to promote efficient switching operation thereof.